IWLPC - International Wafer-Level Packaging Conference
The conference includes three tracks with two days of papers covering: Wafer Level Packaging; 3-D (Stacked) Packaging; and MEMS Packaging.
| What |
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|---|---|
| When |
Oct 11, 2010 09:00 AM
to Oct 14, 2010 06:00 PM |
| Where | Santa Clara, CA, USA |
| Add event to calendar |
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Wafer Level Packaging:
- Wafer Level Chip Scale Packaging (WLCSP),
- Flip Chip Bumping
- Fan-Out and Redistribution
- Markets and Trends
- Metrology and Testing
- Wafer and Device Cleaning
- WL-Enabled Devices
- Nanotechnology
- Quality, Reliability, and COO
MEMS Packaging:
- MEMS Processes and Materials
- MEMS Design Tools or Methods
- Nano-MEMS and Bio-MEMS
- MOEMS Integration
- Lab-on-Chip
3-D Integration:
- 3D WLP
- Thru Silicon Vias (TSV)
- Silicon Interposers
- Wafer Thinning and Handling
- Stacking Processes (W2W,D2W,D2D)
- IC Packaging Substrate
- SIP/SOP vs. SOC
- Mixed Chip Integration Issues
- Embedded Die and Passives
- Modeling & Simulation Tools and Methods
- TSV Integration: FEOL vs BEOL
- Metrology and Testing
- Reliability and Inspection
Measurements in space
